A dynamic random access memory (DRAM) is a type of semiconductor memory device. In general, a DRAM device includes a field effect transistor that controls read/write operations and a capacitor that stores an electric charge. The integration density of DRAMs has been regularly increased by, for example, miniaturizing the field effect transistor and/or forming capacitors having a desired capacitance in smaller regions. For example, technology has been developed for forming a stack capacitor or a deep trench capacitor. However, short channel effects due to the miniaturization of the transistor and/or an increase in the manufacturing cost due to the complicated process of forming the capacitor may make it difficult to further increase the integration density of DRAMs.
Providing a single transistor DRAM cell without a capacitor or a floating body cell (FBC) formed on a semiconductor layer of a silicon-on-insulator (SOI) substrate have been proposed as possible approaches for reducing the complexity of the process of forming a DRAM cell.
FIG. 1 is a sectional view illustrating a structure of a conventional single transistor DRAM cell without a capacitor.
Referring to FIG. 1, a single transistor DRAM cell 100 includes: a substrate 15 having a silicon substrate 10 and a silicon oxide layer 20 formed on the silicon substrate 10. A P-type body region 31, an N-type source region 32, and an N-type drain region 33 are formed in a silicon layer 30 on the silicon oxide layer 20. The N-type source region 32 and the N-type drain region 33 extend through the thickness of the silicon layer 30. The P-type body region 31 is formed between the N-type source region 32 and the N-type drain region 33. The P-type body region 31 is an electrically floating region that is bounded by the silicon oxide layer 20 and its junction with the N-type source region 32 and the N-type drain region 33. A gate insulating film 50 and a gate electrode 60 are disposed on the P-type body region 31.
The P-type body region 31 of the single transistor DRAM cell 100 is capable of storing an electric charge. The single transistor DRAM cell 100 experiences a change in a current between the source/drain regions and/or a change in the threshold voltage of the device, depending on the density of excess carriers accumulated in the floating P-type body region 31. By detecting such changes, the programming state of the memory cell may be determined. Thus, the device 100 may not require a capacitor to be formed. Accordingly, it may be possible to enhance the integration density of DRAMs and/or to economically fabricate DRAMs using such a structure. However, the performance of the memory device may degrade due to short channel effects, as the channel length of the transistor is reduced.
In order to address the short channel effects due to reduced channel length of a single transistor DRAM cell, a method of increasing the impurity concentration in a channel region and a body region of a DRAM cell and decreasing the thickness of a semiconductor layer is disclosed in “Memory Design Using a One-Transistor Gain Cell on SOI” of T. Ohsawa et al., IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 37, pp. 1510-1522, 2002. However, when the impurity concentration of the channel and the body region increases, leakage current may increase more in a junction region, thereby reducing the charge retention time of the DRAM cell. Also, the volume of a floating body decreases with the increase of the integration density, and thus the concentration of the stored excess carriers (holes or electrons) may decrease. Accordingly, the charge capacity required by a DRAM may not be obtained.